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Hardware Error Correction

computer data storage that can detect and correct the most common kinds of internal data corruption. ECC memory is used in most computers where data corruption cannot be

Inhibit Operation

tolerated under any circumstances, such as for scientific or financial computing. Typically, ECC what is elliptic curve cryptography memory maintains a memory system immune to single-bit errors: the data that is read from each word is always the error correction code algorithm same as the data that had been written to it, even if one or more bits actually stored have been flipped to the wrong state. Most non-ECC memory cannot detect errors although http://www.ibm.com/support/knowledgecenter/SSB23S_1.1.0.13/gtpn1/gtpn1mst23.html some non-ECC memory with parity support allows detection but not correction. Contents 1 Problem background 2 Solutions 3 Implementations 4 Cache 5 Registered memory 6 Advantages and disadvantages 7 References 8 External links Problem background[edit] Electrical or magnetic interference inside a computer system can cause a single bit of dynamic random-access memory (DRAM) to spontaneously flip to the opposite state. It was initially thought that https://en.wikipedia.org/wiki/ECC_memory this was mainly due to alpha particles emitted by contaminants in chip packaging material, but research has shown that the majority of one-off soft errors in DRAM chips occur as a result of background radiation, chiefly neutrons from cosmic ray secondaries, which may change the contents of one or more memory cells or interfere with the circuitry used to read or write to them.[2] Hence, the error rates increase rapidly with rising altitude; for example, compared to the sea level, the rate of neutron flux is 3.5 times higher at 1.5km and 300 times higher at 10–12km (the cruising altitude of commercial airplanes).[3] As a result, systems operating at high altitudes require special provision for reliability. As an example, the spacecraft Cassini–Huygens, launched in 1997, contains two identical flight recorders, each with 2.5gigabits of memory in the form of arrays of commercial DRAM chips. Thanks to built-in EDAC functionality, spacecraft's engineering telemetry reports the number of (correctable) single-bit-per-word errors and (uncorrectable) double-bit-per-word errors. During the first 2.5years of flight, the spacecraft reported a nearly constant single-bit error rate of about 280errors per day. However, on November 6, 1997, during the first month in spa

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